The present invention relates to a method for fabricating a semiconductor device, and more particularly to a method for forming inter-metal dielectrics in a semiconductor device.
Recently the highly integrated semiconductor device tends to have multiple conductive layers, which intensifies the importance of flatness of the insulating layers between the metal layers. In order to achieve the flatness of the insulating layers between the multiple metal layers in a semiconductor device, there are generally used spin-on glass process, etch-back process, or resinous insulating process using polyimide. However these accompany problems such as voids, cracks, etc. produced in the regions between the conductive lines during the planarization process because the conductive lines have increased step differences and the intervals between the conductive lines are in order of submicrons.
There is shown a conventional spin-on glass planarization process in FIGS. 1A-1D. In this case, the starting material is a semiconductor substrate with lower conductive lines 3. The process for forming transistors, capacitors, etc. is neglected in the drawings. Referring to FIG. 1A, a second insulating layer 5 of oxide is deposited over a semiconductor substrate (not shown) with a first insulating layer 1 of BPSG (Boro-Phospho-Silicate Glass) and a first metal layer 3 forming the lower conductive lines. In the step of FIG. 1B, a third insulating layer 7 of spin-on glass is coated and subjected to heat treatment. The third insulating layer is usually coated several times to improve the step coverage and avoid the cracks. In the step of FIG. 1C, the spin-on glass layer 7 is etched-back so as to expose the portions of the insulating layer 5 over the first metal layer 3. In the step of FIG. 1D, a fourth insulating layer 9 for buffering is finally laid over the substrate completing the planarization of the insulating layer between the lower and upper conductive lines. However, the spin-on glass layer 7 is so weak as to be easily cracked, so that the reliability of the semiconductor device could not be secured.